The AI Chip Supply Chain: How It’s Made and Who Controls It

Almost every AI thing you touched today traces back to a few buildings on one island, and one machine that only a single company on earth knows how to build.

I’m a self-taught operator. I run a small California service business on software I wrote myself, and I spend a lot of my day thinking about what my code costs to run. That cost bottoms out in physics — a chip somebody etched, in a fab somebody spent tens of billions to build, using light so precise it barely exists in nature. I went down the rabbit hole on how that whole chain actually works, and it’s wilder and more fragile than the headlines make it sound.

So here’s the map. Who designs the chips, who actually makes them, where, and why the entire AI boom is currently rate-limited by a handful of choke points. And then the part I care about most as a builder: the one place in this chain where you have any control at all.

The stack: who actually does what

First thing that surprised me: the company whose name is on the chip usually didn’t make it. The industry is split into layers, and almost nobody does more than one of them well.

The designers are “fabless” — they draw the chip and own zero factories. Nvidia, AMD, Apple, and now the big cloud players designing their own silicon. Nvidia sits on top of the AI pile hard: it holds somewhere around 80% of the AI accelerator market, on the order of $190 billion in data-center revenue in its 2026 fiscal year. They design the thing. They don’t pour it.

The fab — the factory that turns a design into actual silicon — is where the map collapses onto one company. TSMC in Taiwan runs roughly 70% of the world’s contract chip manufacturing and makes something like 90% of the most advanced chips — the 3-nanometer-and-below stuff that every flagship AI part is built on. Not most of it. Almost all of it.

Then two more layers nobody talks about until they’re the bottleneck. Memory: the fast stacked memory that feeds a GPU, called high-bandwidth memory (HBM), comes from basically three firms — SK Hynix, Samsung, and Micron. And packaging: the step that bolts the logic die and the memory stacks onto one slab so they can talk fast enough. TSMC’s version is called CoWoS, and it turns out to matter as much as the chip itself.

How a chip actually gets made

A chip starts as a disc of ultra-pure silicon called a wafer. To carve a pattern into it you shine light through a stencil onto a light-sensitive coating, wash away what got exposed, and repeat. Do that a few hundred times, layer on layer, and you’ve built billions of transistors on a fingernail of silicon. The catch is the resolution. To draw features a few atoms wide, ordinary light is way too fat.

So the leading edge uses extreme ultraviolet lithography (EUV) — light with a wavelength of 13.5 nanometers, generated by blasting molten tin droplets with a laser fifty thousand times a second. Only one company builds the machines that do this: ASML in the Netherlands. Not “leads the market.” The only one. Their next-gen High-NA machine runs about $400 million a unit, and it’s so expensive that TSMC has said it’s sticking with its current EUV tools and a trick called multi-patterning — exposing the same wafer several times to fake the finer detail — rather than buy in yet.

The triple squeeze: why chips are sold out

Here’s the thing people miss when they ask why they can’t get GPUs. It isn’t one shortage. It’s three, stacked, and a chip needs all three to ship. The industry calls it the triple constraint:

TSMC’s newest 2nm process (they call it N2) started volume production around Q3 2026, with Nvidia, Apple, and AMD as the anchor customers. The frontend capacity for it is essentially spoken for through 2027. Even when the raw logic is available, the packaging step is its own bottleneck — you can etch the die and still wait months for a CoWoS slot to marry it to its memory. That’s why “we have the chips” and “we can ship the chips” are two very different sentences right now.

Who controls it, and where it’s moving

Add it up and control is startlingly concentrated. Nvidia owns the demand side of AI compute. TSMC owns the making. ASML owns the machine that makes the making possible. Three companies, three countries, one long thin thread — and most of the critical manufacturing sitting on an island that a lot of very nervous governments would rather it didn’t all sit on.

That nervousness is the story of the next five years. TSMC is spending about $165 billion building fabs in Arizona. The first one started production in 2025 and is already making silicon for Nvidia’s Blackwell parts — the first time TSMC has made its most advanced chips anywhere outside Taiwan. There’s more going up in Japan and Germany. The U.S. CHIPS Act and its equivalents abroad are all chasing the same goal: stop having a single earthquake, or a single blockade, be able to switch off the modern economy.

It’s real diversification, and it’s slow. Fabs take years and the expertise doesn’t copy-paste. For a while yet, “where AI chips come from” still mostly answers to one address.

The one part you control: your code

Here’s where I bring it home, because everything above is out of your hands. You’re not going to build a fab. You can’t call ASML. But the silicon is the single most expensive, most rationed thing in your whole stack — and whether you actually use it or waste it is entirely a software decision. I see people rent a GPU that cost more than a car and then feed it work one crumb at a time, on the CPU, while the expensive part sits there doing nothing.

This is the version almost everybody writes first. It runs. It’s also leaving most of the machine idle.

// BAD — one item at a time, on the CPU. the GPU you’re paying for sits idle.

Same model, same math, three small changes: hand the GPU a whole batch at once instead of one item, actually move the work onto the device, and drop the numbers to half precision so twice as many fit. On real workloads that’s the difference between a job that takes all night and one that’s done before coffee.

// GOOD — batch it, move it onto the GPU, run fp16. same model, far more throughput.

Two things earn most of the win. Batching means the GPU works on 256 items in parallel instead of stalling between single calls — that’s the entire reason the hardware is shaped the way it is. And torch.inference_mode() tells the framework you’re not training, so it stops building the bookkeeping graph it’d need for gradients and hands that memory back to your actual work.

That’s the honest takeaway from staring at this whole chain. The supply side is a marvel you and I have no say over. The demand side, the code, the part that decides whether a rationed chip does a full day’s work or a tenth of one — that’s the only lever in the whole system with your hand on it. So use it.

FAQ

Why does TSMC make almost all the advanced chips?

Cutting-edge fabs cost tens of billions and take years, and the process knowledge — running EUV machines at high yield — barely transfers. TSMC got there first at scale, so the whole industry designs around them. That’s why one company ended up making roughly 90% of the leading-edge silicon.

What is the “triple constraint” on AI chips?

Three separate bottlenecks a chip needs all at once: 2nm logic capacity, CoWoS advanced packaging, and HBM memory. Any one being short stops the chip from shipping, and in 2026 all three are tight.

Will Arizona fabs fix the supply problem?

They help, but slowly. TSMC’s Arizona build is real and already making advanced parts, yet fabs take years to ramp and the expertise doesn’t copy overnight. For a while the leading edge still mostly lives in Taiwan.

If you want the builder side of how I actually run on this stuff, I wrote up the voice AI that lives in my headset, how I built an AI agent that audits my own code, and how I coded an assistant that runs my business by voice and text. And if you want the other half of my brain, the music side is where the guitars live — start with Songs I Can Play.